Unexpected high write bandwidth ratio despite low setRatio

[yunjeongmun]

Hi, I'm yunjeong.

When running cachebench with getRatio=0.95, setRatio=0.05, and touchValue=true, the measured memory bandwidth shows ~97% write and only ~3% read, which is unexpected.
We also observed 99% write bandwidth with getRatio=0.5, setRatio=0.5.

Expected Behavior

• measurable DRAM read traffic, about 60~70%

Version:

• commit efa4506

Configuration

  {
    "cache_config": {
      "cacheSizeMB": 150120,
      "memoryTiers": [{"ratio": 1}],
      "numPools": 1,
      "poolSizes": [1.0],
      "maxAllocSize": 4194304,
      "touchValue": true
    },
    "test_config": {
      "numOps": 6000000,
      "numThreads": 96,
      "numKeys": 50000,
      "keySizeRange": [1, 8, 64],
      "keySizeRangeProbability": [0.3, 0.7],
      "valSizeRange": [2097152],
      "valSizeRangeProbability": [1.0],
      "getRatio": 0.95,
      "setRatio": 0.05,
      "delRatio": 0.0
    }
  }

Observed Metrics:

• cachebench hit ratio: 88.6%
• DRAM Read: ~6000MB/s
• DRAM Write: ~200,000 MB/s
• DRAM Read ratio: ~3%
• DRAM Write ratio: ~97%

Below is the average memory throughput during the cachebench execution.
It was measured using the bwprof tool based on Intel PCM.

    Socket0        Throughput   AccessTotal    MemAccess  MediaAccess
                         MB/s            GB        Ratio        Ratio
    DRAM   Read       4295.51        365.12         2.5%            -
           Write    167865.37      14268.56        97.5%            -
           Total    172160.87      14633.67            -       100.0%
    CXL    Read          0.00          0.00         0.0%            -
           Write         0.11          0.01       100.0%            -
           Total         0.11          0.01            -         0.0%

    Socket1        Throughput   AccessTotal    MemAccess  MediaAccess
                         MB/s            GB        Ratio        Ratio
    DRAM   Read       6131.75        521.20         3.2%            -
           Write    187378.09      15927.14        96.8%            -
           Total    193509.84      16448.34            -       100.0%
    CXL    Read          0.02          0.00        20.7%            -
           Write         0.10          0.01        79.3%            -
           Total         0.12          0.01            -         0.0%

1. Is this behavior expected?
2. Are there additional setting required to ensure generates measurable DRAM read traffic?

Thanks!