cpu_5.15.1.patch

diff -Naur a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
--- a/arch/x86/Kconfig.cpu	2021-11-06 13:13:31.000000000 +0000
+++ b/arch/x86/Kconfig.cpu	2021-11-08 15:12:29.651764303 +0000
@@ -32,6 +32,17 @@
 	  - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
 	  - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
 	  - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs.
+	  - "AMD Opteron/Athlon64/Hammer/K7 with SSE3" for AMD Improved K8-family.
+	  - "AMD 61xx/7x50/PhenomX3/X4/II/K10" for AMD K10-family.
+	  - "AMD Barcelona" for AMD Family 10h.
+	  - "AMD Bobcat" for AMD Family 14h.
+	  - "AMD Jaguar" for AMD Family 16h.
+	  - "AMD Bulldozer" for AMD Family 15h.
+	  - "AMD Piledriver" for AMD Family 15h.
+	  - "AMD Streamroller" for AMD Family 15h.
+	  - "AMD Excavator" for AMD Family 15h.
+	  - "AMD Zen" for AMD Family 17h.
+	  - "AMD Zen (gen 2)" for AMD Family 17h.
 	  - "Crusoe" for the Transmeta Crusoe series.
 	  - "Efficeon" for the Transmeta Efficeon series.
 	  - "Winchip-C6" for original IDT Winchip.
@@ -45,6 +56,21 @@
 	  - "Intel P4" for the Pentium 4/Netburst microarchitecture.
 	  - "Core 2/newer Xeon" for all core2 and newer Intel CPUs.
 	  - "Intel Atom" for the Atom-microarchitecture CPUs.
+	  - "Intel Silvermont" for Intel Silvermont low-power processors.
+	  - "Intel Nehalem" for Intel 1st Gen Core i3/i5/i7.
+	  - "Intel Westmere" for Intel 1.5 Gen Core i3/i5/i7.
+	  - "Intel Sandybridge" for Intel 2nd Gen Core i3/i5/i7.
+	  - "Intel Ivybridge" for Intel 3rd Gen Core i3/i5/i7.
+	  - "Intel Haswell" for Intel 4th Gen Core i3/i5/i7.
+	  - "Intel Broadwell" for Intel 5th Gen Core i3/i5/i7.
+	  - "Intel Skylake" for Intel 6th Gen Core i3/i5/i7.
+	  - "Intel Skylake X" for Intel 6th Gen Core i7/i9.
+	  - "Intel Cannonlake" for Intel 8th Gen Core i3/i5/i7.
+	  - "Intel Icelake" for Intel 8th Gen Core i7/i9.
+	  - "Intel Cascadelake"
+	  - "Intel Cooperlake"
+	  - "Intel Tigerlake"
+	  - "Native" for a gcc automatic optimization.
 	  - "Generic-x86-64" for a kernel which runs on any x86-64 CPU.
 
 	  See each option's help text for additional details. If you don't know
@@ -81,14 +107,14 @@
 
 config M586MMX
 	bool "Pentium-MMX"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_INTEL)
 	help
 	  Select this for a Pentium with the MMX graphics/multimedia
 	  extended instructions.
 
 config M686
 	bool "Pentium-Pro"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_INTEL)
 	help
 	  Select this for Intel Pentium Pro chips.  This enables the use of
 	  Pentium Pro extended instructions, and disables the init-time guard
@@ -96,7 +122,7 @@
 
 config MPENTIUMII
 	bool "Pentium-II/Celeron(pre-Coppermine)"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_INTEL)
 	help
 	  Select this for Intel chips based on the Pentium-II and
 	  pre-Coppermine Celeron core.  This option enables an unaligned
@@ -106,7 +132,7 @@
 
 config MPENTIUMIII
 	bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_INTEL)
 	help
 	  Select this for Intel chips based on the Pentium-III and
 	  Celeron-Coppermine core.  This option enables use of some
@@ -115,14 +141,14 @@
 
 config MPENTIUMM
 	bool "Pentium M"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_INTEL)
 	help
 	  Select this for Intel Pentium M (not Pentium-4 M)
 	  notebook chips.
 
 config MPENTIUM4
 	bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_INTEL)
 	help
 	  Select this for Intel Pentium 4 chips.  This includes the
 	  Pentium 4, Pentium D, P4-based Celeron and Xeon, and
@@ -158,7 +184,7 @@
 
 config MK6
 	bool "K6/K6-II/K6-III"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_AMD)
 	help
 	  Select this for an AMD K6-family processor.  Enables use of
 	  some extended instructions, and passes appropriate optimization
@@ -166,7 +192,7 @@
 
 config MK7
 	bool "Athlon/Duron/K7"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_AMD)
 	help
 	  Select this for an AMD Athlon K7-family processor.  Enables use of
 	  some extended instructions, and passes appropriate optimization
@@ -174,14 +200,105 @@
 
 config MK8
 	bool "Opteron/Athlon64/Hammer/K8"
+    depends on CPU_SUP_AMD
 	help
 	  Select this for an AMD Opteron or Athlon64 Hammer-family processor.
 	  Enables use of some extended instructions, and passes appropriate
 	  optimization flags to GCC.
+	  
+config MK8SSE3
+	bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
+	  Enables use of some extended instructions, and passes appropriate
+	  optimization flags to GCC.
+
+config MK10
+	bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
+		Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
+	  Enables use of some extended instructions, and passes appropriate
+	  optimization flags to GCC.
+
+config MBARCELONA
+	bool "AMD Barcelona"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 10h Barcelona processors.
+
+	  Enables march=barcelona
+
+config MBOBCAT
+	bool "AMD Bobcat"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 14h Bobcat processors.
+
+	  Enables march=btver1
+
+config MJAGUAR
+	bool "AMD Jaguar"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 16h Jaguar processors.
+
+	  Enables march=btver2
+
+config MBULLDOZER
+	bool "AMD Bulldozer"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 15h Bulldozer processors.
 
+	  Enables march=bdver1
+
+config MPILEDRIVER
+	bool "AMD Piledriver"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 15h Piledriver processors.
+
+	  Enables march=bdver2
+
+config MSTEAMROLLER
+	bool "AMD Steamroller"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 15h Steamroller processors.
+
+	  Enables march=bdver3
+
+config MEXCAVATOR
+	bool "AMD Excavator"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 15h Excavator processors.
+
+	  Enables march=bdver4
+
+config MZEN1
+	bool "AMD Zen"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 17h Zen processors.
+
+	  Enables march=znver1
+
+config MZEN2
+	bool "AMD Zen 2 gen"
+	depends on CPU_SUP_AMD
+	help
+	  Select this for AMD Family 17h Zen processors.
+
+	  Enables march=znver2	  
+
+	  
 config MCRUSOE
 	bool "Crusoe"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_TRANSMETA_32)
 	help
 	  Select this for a Transmeta Crusoe processor.  Treats the processor
 	  like a 586 with TSC, and sets some GCC optimization flags (like a
@@ -189,7 +306,7 @@
 
 config MEFFICEON
 	bool "Efficeon"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_TRANSMETA_32)
 	help
 	  Select this for a Transmeta Efficeon processor.
 
@@ -213,7 +330,7 @@
 
 config MELAN
 	bool "AMD Elan"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_AMD)
 	help
 	  Select this for an AMD Elan processor.
 
@@ -221,13 +338,13 @@
 
 config MGEODEGX1
 	bool "GeodeGX1"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_AMD)
 	help
 	  Select this for a Geode GX1 (Cyrix MediaGX) chip.
 
 config MGEODE_LX
 	bool "Geode GX/LX"
-	depends on X86_32
+	depends on (X86_32 && CPU_SUP_AMD)
 	help
 	  Select this for AMD Geode GX and LX processors.
 
@@ -260,7 +377,8 @@
 
 config MPSC
 	bool "Intel P4 / older Netburst based Xeon"
-	depends on X86_64
+	select X86_P6_NOP
+	depends on (X86_64 && CPU_SUP_INTEL)
 	help
 	  Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
 	  Xeon CPUs with Intel 64bit which is compatible with x86-64.
@@ -271,6 +389,8 @@
 
 config MCORE2
 	bool "Core 2/newer Xeon"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
 	help
 
 	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
@@ -280,12 +400,147 @@
 
 config MATOM
 	bool "Intel Atom"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
 	help
 
 	  Select this for the Intel Atom platform. Intel Atom CPUs have an
 	  in-order pipelining architecture and thus can benefit from
 	  accordingly optimized code. Use a recent GCC with specific Atom
 	  support in order to fully benefit from selecting this option.
+config MNEHALEM
+	bool "Intel Nehalem"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+ 
+	  Select this for 1st Gen Core processors in the Nehalem family.
+
+	  Enables march=nehalem
+
+config MWESTMERE
+	bool "Intel Westmere"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for the Intel Westmere formerly Nehalem-C family.
+
+	  Enables march=westmere
+
+config MSILVERMONT
+	bool "Intel Silvermont"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for the Intel Silvermont platform.
+
+	  Enables march=silvermont
+
+config MSANDYBRIDGE
+	bool "Intel Sandy Bridge"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for 2nd Gen Core processors in the Sandy Bridge family.
+
+	  Enables march=sandybridge
+
+config MIVYBRIDGE
+	bool "Intel Ivy Bridge"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for 3rd Gen Core processors in the Ivy Bridge family.
+
+	  Enables march=ivybridge
+
+config MHASWELL
+	bool "Intel Haswell"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for 4th Gen Core processors in the Haswell family.
+
+	  Enables march=haswell
+
+config MBROADWELL
+	bool "Intel Broadwell"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for 5th Gen Core processors in the Broadwell family.
+
+	  Enables march=broadwell
+
+config MSKYLAKE
+	bool "Intel Skylake"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for 6th Gen Core processors in the Skylake family.
+
+	  Enables march=skylake
+
+config MSKYLAKEX
+	bool "Intel Skylake X"
+ 	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for 6th Gen Core processors in the Skylake X family.
+
+	  Enables march=skylake-avx512
+
+config MCANNONLAKE
+	bool "Intel Cannonlake"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for 8th Gen Core processors
+
+	  Enables march=cannonlake
+
+config MICELAKE
+	bool "Intel Icelake"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Select this for 8th Gen Core processors in the Ice Lake family.
+
+	  Enables march=icelake
+	  
+config MCASCADELAKE
+	bool "Intel Cascadelake"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+
+	  Enables march=cascadelake
+	  
+config MCOOPERLAKE
+	bool "Intel Cooperlake"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+	
+	  Enables march=cooperlake
+	  
+config MTIGERLAKE
+	bool "Intel Tigerlake"
+	depends on CPU_SUP_INTEL
+	select X86_P6_NOP
+	help
+	  
+	  Enables march=tigerlake
 
 config GENERIC_CPU
 	bool "Generic-x86-64"
@@ -294,6 +549,17 @@
 	  Generic x86-64 CPU.
 	  Run equally well on all x86-64 CPUs.
 
+config MNATIVE
+    bool "Native optimizations autodetected by GCC"
+    help
+	  GCC 4.2 and above support -march=native, which automatically detects
+	  the optimum settings to use based on your processor. -march=native
+	  also detects and applies additional settings beyond -march specific
+	  to your CPU. But a compiled kernel may not work on earlier or other 
+	  CPU architectures, be aware.
+	  
+	  Enables march=native
+
 endchoice
 
 config X86_GENERIC
@@ -318,7 +584,7 @@
 config X86_L1_CACHE_SHIFT
 	int
 	default "7" if MPENTIUM4 || MPSC
-	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
+	default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN1 || MZEN2 || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MTIGERLAKE || MCOOPERLAKE || MCASCADELAKE || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
 	default "4" if MELAN || M486SX || M486 || MGEODEGX1
 	default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
 
@@ -336,45 +602,46 @@
 
 config X86_INTEL_USERCOPY
 	def_bool y
-	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
+	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MTIGERLAKE || MCOOPERLAKE || MCASCADELAKE || MNATIVE
 
 config X86_USE_PPRO_CHECKSUM
 	def_bool y
-	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
+	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MTIGERLAKE || MCOOPERLAKE || MCASCADELAKE || MATOM || MNATIVE
 
 config X86_USE_3DNOW
 	def_bool y
 	depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
 
-#
-# P6_NOPs are a relatively minor optimization that require a family >=
-# 6 processor, except that it is broken on certain VIA chips.
-# Furthermore, AMD chips prefer a totally different sequence of NOPs
-# (which work on all CPUs).  In addition, it looks like Virtual PC
-# does not understand them.
-#
-# As a result, disallow these if we're not compiling for X86_64 (these
-# NOPs do work on all x86-64 capable chips); the list of processors in
-# the right-hand clause are the cores that benefit from this optimization.
-#
 config X86_P6_NOP
-	def_bool y
-	depends on X86_64
-	depends on (MCORE2 || MPENTIUM4 || MPSC)
+	default y
+	bool "Support for P6_NOPs on Intel chips"
+	depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT  || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MTIGERLAKE || MCOOPERLAKE || MCASCADELAKE || MNATIVE)
+	help
+	P6_NOPs are a relatively minor optimization that require a family >=
+	6 processor, except that it is broken on certain VIA chips.
+	Furthermore, AMD chips prefer a totally different sequence of NOPs
+	(which work on all CPUs).  In addition, it looks like Virtual PC
+	does not understand them.
+
+	As a result, disallow these if we're not compiling for X86_64 (these
+	NOPs do work on all x86-64 capable chips); the list of processors in
+	the right-hand clause are the cores that benefit from this optimization.
+
+	Say Y if you have Intel CPU newer than Pentium Pro, N otherwise.
 
 config X86_TSC
 	def_bool y
-	depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
+	depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MTIGERLAKE || MCOOPERLAKE || MCASCADELAKE || MNATIVE || MATOM || X86_64)
 
 config X86_CMPXCHG64
 	def_bool y
-	depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8
+	depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN1 || MZEN2 || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MTIGERLAKE || MCOOPERLAKE || MCASCADELAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX)
 
 # this should be set for all -march=.. options where the compiler
 # generates cmov.
 config X86_CMOV
 	def_bool y
-	depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
+	depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN1 || MZEN2 || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MCANNONLAKE || MICELAKE || MTIGERLAKE || MCOOPERLAKE || MCASCADELAKE || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX)
 
 config X86_MINIMUM_CPU_FAMILY
 	int
diff -Naur a/arch/x86/Makefile b/arch/x86/Makefile
--- a/arch/x86/Makefile	2021-11-06 13:13:31.000000000 +0000
+++ b/arch/x86/Makefile	2021-11-08 15:14:14.814527921 +0000
@@ -48,7 +48,7 @@
 #
 #    https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53383
 #
-KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx
+KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-3dnow -mno-avx
 
 # Intel CET isn't enabled in the kernel
 KBUILD_CFLAGS += $(call cc-option,-fcf-protection=none)
@@ -117,11 +117,68 @@
 	KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup)
 
         # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
-        cflags-$(CONFIG_MK8)		+= -march=k8
-        cflags-$(CONFIG_MPSC)		+= -march=nocona
-        cflags-$(CONFIG_MCORE2)		+= -march=core2
-        cflags-$(CONFIG_MATOM)		+= -march=atom
-        cflags-$(CONFIG_GENERIC_CPU)	+= -mtune=generic
+        cflags-$(CONFIG_MNATIVE) += \
+                $(call cc-option,-march=native)
+        cflags-$(CONFIG_MK8) += \
+                $(call cc-option,-march=k8,$(call cc-option,-mtune=k8))
+        cflags-$(CONFIG_MK8SSE3) += \
+                $(call cc-option,-march=k8-sse3,$(call cc-option,-mtune=k8-sse3))
+        cflags-$(CONFIG_MK10) += \
+                $(call cc-option,-march=amdfam10,$(call cc-option,-mtune=amdfam10))
+        cflags-$(CONFIG_MBARCELONA) += \
+                $(call cc-option,-march=barcelona,$(call cc-option,-mtune=barcelona))
+        cflags-$(CONFIG_MBOBCAT) += \
+                $(call cc-option,-march=btver1,$(call cc-option,-mtune=btver1))
+        cflags-$(CONFIG_MJAGUAR) += \
+                $(call cc-option,-march=btver2,$(call cc-option,-mtune=btver2))
+        cflags-$(CONFIG_MBULLDOZER) += \
+                $(call cc-option,-march=bdver1,$(call cc-option,-mtune=bdver1))
+        cflags-$(CONFIG_MPILEDRIVER) += \
+                $(call cc-option,-march=bdver2,$(call cc-option,-mtune=bdver2))
+        cflags-$(CONFIG_MSTEAMROLLER) += \
+                $(call cc-option,-march=bdver3,$(call cc-option,-mtune=bdver3))
+        cflags-$(CONFIG_MEXCAVATOR) += \
+                $(call cc-option,-march=bdver4,$(call cc-option,-mtune=bdver4))
+        cflags-$(CONFIG_MZEN1) += \
+                $(call cc-option,-march=znver1,$(call cc-option,-mtune=znver1))
+        cflags-$(CONFIG_MZEN2) += \
+                $(call cc-option,-march=znver2,$(call cc-option,-mtune=znver2))
+        cflags-$(CONFIG_MPSC) += \
+                $(call cc-option,-march=nocona,$(call cc-option,-mtune=nocona))
+        cflags-$(CONFIG_MCORE2) += \
+                $(call cc-option,-march=core2,$(call cc-option,-mtune=core2))
+        cflags-$(CONFIG_MNEHALEM) += \
+                $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem))
+        cflags-$(CONFIG_MWESTMERE) += \
+                $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere))
+        cflags-$(CONFIG_MSILVERMONT) += \
+                $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont))
+        cflags-$(CONFIG_MSANDYBRIDGE) += \
+                $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge))
+        cflags-$(CONFIG_MIVYBRIDGE) += \
+                $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge))
+        cflags-$(CONFIG_MHASWELL) += \
+                $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell))
+        cflags-$(CONFIG_MBROADWELL) += \
+                $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell))
+        cflags-$(CONFIG_MSKYLAKE) += \
+                $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake))
+        cflags-$(CONFIG_MSKYLAKEX) += \
+                $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512))
+        cflags-$(CONFIG_MCANNONLAKE) += \
+                $(call cc-option,-march=cannonlake,$(call cc-option,-mtune=cannonlake))
+        cflags-$(CONFIG_MICELAKE) += \
+                $(call cc-option,-march=icelake,$(call cc-option,-mtune=icelake))
+        cflags-$(CONFIG_MCASCADELAKE)+= \
+                $(call cc-option,-march=cascadelake,$(call cc-option,-mtune=cascadelake))
+        cflags-$(CONFIG_MCOOPERLAKE)+= \
+                $(call cc-option,-march=cooperlake,$(call cc-option,-mtune=cooperlake))
+        cflags-$(CONFIG_MTIGERLAKE)+= \
+                $(call cc-option,-march=tigerlake,$(call cc-option,-mtune=tigerlake))
+        cflags-$(CONFIG_MATOM) += \
+                $(call cc-option,-march=bonnell,$(call cc-option,-mtune=bonnell),$(call cc-option,-mtune=generic))
+        cflags-$(CONFIG_GENERIC_CPU) += \
+                $(call cc-option,-mtune=generic)
         KBUILD_CFLAGS += $(cflags-y)
 
         KBUILD_CFLAGS += -mno-red-zone