decoder: Add formal-style safety assertions for control, memory, and illegal instruction handling

[Anubhav-30]

This PR introduces a set of safety assertions in the decoder to
improve verification and ensure correct control behavior.

The assertions cover:

• No register writes on illegal instructions
• No memory requests during illegal or branch conditions
• Mutual exclusion of branch and jump signals
• No CSR access on illegal instructions
• No register reads on illegal instructions

These checks align the decoder behavior with real hardware
verification practices and improve robustness against unintended
side effects.

This enhances confidence in control-path correctness and makes
the design more verification-friendly.