"Enhance decoder safety for illegal instructions + Add verification testbench"#2389
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Anubhav-30 wants to merge 1 commit intolowRISC:masterfrom
Open
"Enhance decoder safety for illegal instructions + Add verification testbench"#2389Anubhav-30 wants to merge 1 commit intolowRISC:masterfrom
Anubhav-30 wants to merge 1 commit intolowRISC:masterfrom
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This PR improves decoder robustness by fully disabling side-effect signals
during illegal instruction detection.
Additionally, a SystemVerilog testbench is added to verify that no register,
memory, or control signals are unintentionally activated.
This ensures safer pipeline behavior and improves verification coverage.