Add Comprehensive Safety Assertions for Illegal Instruction Handling in Decoder

[Anubhav-30]

This PR enhances decoder robustness by adding assertion-based safety checks.

The assertions ensure that no unintended side effects occur when an illegal
instruction is detected, including:

• No register file reads
• No memory access requests
• No control flow changes
• No CSR access

A SystemVerilog testbench is also added to validate these safety conditions.

This improves verification coverage and aligns with formal verification practices.

[azure-pipelines]

Azure Pipelines:
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